Mass storage is used to store large amounts of data that is typically copied to a faster random-access memory such as a dynamic-random-access memory (DRAM) for use by a processor. While the processor's DRAM is randomly accessible, mass storage is block-accessible. An entire block of data must be read or written from the mass storage device. A RAM may allow reading and writing of individual bytes or words of 4 or 8 bytes, while a mass storage device requires that a sector or 512 bytes or more be read or written together.
Solid-State Drives (SSD) contain flash memory and may be used as a mass storage device in lieu of a hard disk. Flash-memory arrays are also block-accessible, but have a much faster access time than rotating media such as a hard disk. However, since flash memory chips are block-addressable rather than randomly-accessible, flash is not as easy to use for a cache as DRAM or SRAM.
While an entire block has to be erased together, pages within a block could be written and over-written several times. Some older flash memory chips may allow over-writing of pages that have previously been written. Blocks with all stale pages could be erased and re-used.
Older flash memory chips used electrically-erasable programmable read-only memory (EEPROM) memory cells that stored one bit of data per memory cell. Each cell could be in one of two states. When the floating gate in the flash memory cell was charged with electrons, a higher (more positive) gate voltage is needed to turn on the conducting transistor channel. When the floating gate in the flash memory cell was not charged with electrons, a lower (less positive) gate voltage is needed to turn on the conducting transistor channel.
Newer flash memory chips use EEPROM memory cells that store two, four, or more bits of data per memory cell. Different amounts of charge stored on the floating gates produce different current and different sensing voltages for the same memory cell. Thus a single memory cell can store multiple bits of information by assigning different voltages to different logic levels.
Higher density flash memory use multiple voltage levels to store more than one bit per physical flash memory cell. Older Single-Level-Cell (SLC) flash stored just one binary bit per memory cell. Multi-Level-Cell (MLC) stores two bits per cell by having four voltage levels correspond to the four possible logic states of the two binary bits. Triple-Level-Cell (TLC) flash memories store three binary bits per physical cell, and have eight possible logic states and 8 voltage levels. Quad-Level-Cell (QLC) flash memories store four binary bits per physical cell, and have sixteen possible logic states and 16 voltage levels. Other flash types may have more binary bits per memory cell.
Having many logic levels per cell reduces the voltage difference between logic states, resulting in a reduced noise margin. Thus higher-density cells tend to have a lower reliability. Programming must be more exact since the voltage range of any one logic state is smaller, and this precise programming may require more time, and may create more wear on the memory cells, resulting in a lower endurance, or number of program-erase cycles before the cell wears out and fails.
As process technologies shrink the size of the flash memory cell, insulating oxide layers are also shrunk, causing the memory cells to wear out and fail after a smaller number of program-erase cycles. Newer flash chips may only allow for a few thousand or even a few hundred program-erase cycles before the cells become unreliable. Cell leakage also may become a problem.
What is desired is a flash memory system that allows some pages to be programmed as higher-density TLC or MLC, and other pages to be programmed as more reliable SLC. A flash controller that adjusts voltage levels is desirable to allow for more reliable reading of flash cells that have been programmed as TLC, MLC, or SLC cells. A dynamic flash controller that can control a hybrid flash memory with blocks of TLC, MLC, and SLC memory is desirable. A flash controller that refreshes flash memory cells to allow for some leakage over time is also desirable.